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? semiconductor MSM7620 1/28 ? semiconductor MSM7620 echo canceller general description the MSM7620 is an improved version of the msm7520 with the same basic configuration. the MSM7620 includes following improvements: a modified through mode, timing control of the control pin input, and a thinner package. the MSM7620 also provides a pin-for-pin replacement with the msm7520. the MSM7620 is a low-power cmos ic device for cancelling echo (in an acoustic system or telephone line) generated in a speech path. echo is cancelled (in digital signal processing) by estimating the echo path and generating a pseudo-echo signal. used as an acoustic echo canceller, the MSM7620 cancels the acoustic echo between the loud speaker and the microphone which occurs during hands free communication, such as on a car phone or a conference system phone. used as a line echo canceller, the device cancels the line echo impedance mismatching in a hybrid. in addition, a quality conversation is made possible by controlling the level and preventing howling with a howling detector, double talk detector, attenuation function and a gain control function, and by controlling the silence level with a center clipping function. the MSM7620 i/o interface supports m -law pcm. the use of a single chip codec, such as the msm7543, allows the configuration an economic and efficient echo canceller to be configured. features ? handles both acoustic echoes and telephone line echoes. ? cancellable echo delay time: MSM7620-001 ................. for a single chip: 27 ms (max.) MSM7620-011 ................. for a cascade connection (can also be used for a single chip) master chip: 27 ms (max.) slave chip: 31 ms (max.) cancelable up to 213 ms (one master plus six slaves) for a single chip: 27 ms (max.) ? echo attenuation : 30 db (typ.) ? clock frequency : 18 mhz (36 mhz cannot be used) external input and internal oscillator circuit are provided. ? power supply voltage : 5 v (4.5 v to 5.5 v) ? power consumption : 150 mw (typ.) when powered down: 20 mw (typ.) ? package options: 32-pin plastic ssop (ssop32-p-640-0.80-k) (product name : MSM7620-001gs-k) 64-pin plastic qfp (qfp64-p-1414-0.80-bk) (product name : MSM7620-011gs-bk) e2u0038-16-x3 this version: jan. 1998 previous version: nov. 1996
? semiconductor MSM7620 2/28 block diagram MSM7620-001 (single chip only) rin p/s non-linear /linear linear/ non-linear s/p att howling detector double talk detector power calculator adaptive fir filter (aff) s/p linear/ non-linear non-linear /linear p/s center clip clock generator mode selector i/o controller gain att + + C rout sout rst pwdwn sync x1/clkin x2 scko synco nlp hcl adp att gc irld int sck sin wdt v dd v ss MSM7620-011 (cascade connection or single chip) rin p/s non-linear /linear linear/ non-linear s/p att howling detector double talk detector power calculator s/p linear/ non-linear non-linear /linear p/s center clip clock generator mode selector i/o controller gain att + + e rout sout * rst * pwdwn sync x1/clkin * * if the MSM7620-011 is used in the slave mode, only the diagonally hatched blocks and the pins marked with * are used. x2 scko synco nlp hcl * adp att gc irld int * sck sin wdt v dd * v ss * pd15 * pd 0 * of1 * of2 * sf1 * sf2 * ms * parallel i/o port parallel i/o controller adaptive fir filter (aff)
? semiconductor MSM7620 3/28 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32-pin plastic ssop *: no connect pin pin symbol pin symbol pin pin symbol symbol 1 2 3 4 5 6 7 8 * nlp hcl adp v ss att int irld 9 10 11 12 13 14 15 16 sin rin sck sync sout rout * v ss 17 18 19 20 21 22 23 24 * * * x1/clkin x2 * pwdwn synco 25 26 27 28 29 30 31 32 scko * rst wdt gc * * v dd note: pin 26 of the msm7520 is cksel, while that of the MSM7620 is in open state. it is possible to replace the msm7520 with the MSM7620.
? semiconductor MSM7620 4/28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 64-pin plastic ssop note: pins 43, 53, and 61 of the msm7520 are cksel, v dd , and tst2 respectively. while these pins of the MSM7620 are in open state, it is possible to replace the msm7520 with the MSM7620. *: no connect pin pin symbol pin pin symbol symbol pin symbol 1 nlp 17 33 * pd12 49 * 2 hcl 18 34 * pd13 50 * 3 adp 19 35 pd0 x1/clkin 51 pd14 4ms20 36 pd1 x2 52 pd15 5 att 21 37 pd2 * 53 * 6 int 22 38 pd3 pwdwn 54 sf2 7 * 23 39 pd4 * 55 of1 8 irld 24 40 pd5 synco 56 * 9 * 25 41 pd6 scko 57 * 10 sin 26 42 pd7 * 58 * 11 rin 27 43 pd8 * 59 sf1 12 sck 28 44 pd9 rst 60 of2 13 sync 29 45 pd10 wdt 61 * 14 sout 30 46 pd11 gc 62 v dd 15 rout 31 47 *v dd 63 * 16 v ss 32 48 *v dd 64 *
? semiconductor MSM7620 5/28 pin description (1/5) pin 32-pin ssop 64-pin qfp symbol type description 2 1 nlp i the control pin for the center clipping function. this forces the sout output to a minimum value (ff) when the sout signal is below -57 dbm0. effective for reducing low-level noise. ? single chip or master chip in a cascade connection h: center clip on l: center clip off ? slave chip in a cascade connection fixed at l this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. the through mode control. when this pin is in the through mode, rin and sin data are output to rout and sout. at the same time, the coefficient of the adaptive fir filter is cleared. ? single chip or master chip in a cascade connection h: through mode l: normal mode (echo canceller operates) ? slave chip in a cascade connection same as master this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. aff coefficient control pin. this pin stops updating of the adaptive fir filter (aff) coefficient and sets the coefficient to a fixed value, when this pin is configured to be the coefficient fix mode. this pin is used when holding the aff coefficient which has been once converged. ? single chip or master chip in a cascade connection h: coefficient fix mode l: normal mode (coefficient update) ? slave chip in a cascade connection fixed at l this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. selection of the master chip and slave chip when used in a cascade connection. l: single chip or master chip h: slave chip 32 hcl i 4 3 adp i i 4 ms
? semiconductor MSM7620 6/28 (2/5) control for the att function that prevents howling by attenuators (att) for the rin input and sout output. if there is input only to rin, then the att for the sout output is activated. if there is input only to sin, or if there is input to both sin and rin, the att for the rin input is activated. the attenuations of att are approximately 6 db. ? single chip or master chip in a cascade connection h: att off l: att on l is recommended for echo cancellation. ? slave chip in a cascade connection ? fixed at l this input signal is loaded in synchronization with the falling edge of the int signal or the rising edge of the rst signal. interrupt signal which starts 1 cycle (8 khz) of the signal processing. signal processing starts when h-to-l transition is detected. ? single chip or master chip in a cascade connection connect the irld pin. ? slave chip in a cascade connection connect the irld pin of the master chip. int input is invalid for 100 m s after reset due to initialization. refer to the control pin connection example. load detection signal when the sin and rin serial input data are loaded in the internal registers. ? single chip connect to the int pin. ? master chip in a cascade connection connect to the int pin of the master chip and all the slave chips. ? slave chip in a cascade connection leave open. refer to the control pin connection example. transmit serial data. input the m -law pcm signal synchronized to sync and sck. data is read in at the fall of sck. description symbol type pin 32-pin ssop 64-pin qfp 6 5 7 6 88 910 att i int i irld o sin i
? semiconductor MSM7620 7/28 (3/5) receive serial data. input the m -law pcm signal synchronized to sync and sck. data is read in at the fall of sck. pin 32-pin ssop 64-pin qfp symbol type description clock pin for transmit/receive serial data. this pin uses the external sck or the scko. input the pcm codec transmit/receive clock (64 to 2048 khz). sync signal for transmit/receive serial data. this pin uses the external sync or synco. input the pcm codec transmit/receive sync signal (8 khz). transmit serial data. this pin outputs the m -law pcm signal synchronized to sync and sck. this pin is in a high impedance state while there is no data output. receive serial data. this pin outputs the m -law pcm signal synchronized to sync and sck. this pin is in a high impedance state while there is no data output. bidirectional bus for parallel data transfer between the master chip and slave chip when used in a cascade connection. the pd15 pin corresponds to msb. this pin is in a high impedance state while there is no data output. data is loaded in at the falling edge of sfx . power-down mode control. l: power-down mode h: normal operation mode during power-down, all input pins are disabled and output pins are in the following sates : high impedance : sout, rout, pd0 to 15 l: synco, scko h: of1 , of2 holds the last state : wdt, irld not affected: x2, mcko reset after power-down is released. crystal oscilator. leave this pin open if inputting the basic clock externally. this pin is not affected by a reset or power-down. refter to the internal clock generator circuit example. external input for the basic clock or for the crystal oscillator. input the basic clock (18 mhz). refer to the internal clock generator circuit example. rin i 10 11 11 12 sck i 12 13 sync i o sout 13 14 o 14 15 rout i/o 19 30 33 34 51 52 pd0 pd11 pd12 pd13 pd14 pd15 20 35 x1/clkin i 21 36 x2 o 23 38 pwdwn i
? semiconductor MSM7620 8/28 (4/5) input signal for the gain controller when rin input is controlled and the rin input level is controlled and howling is prevented. when this pin is "1" the gain controller starts controlling the level above C24 dbm0 of rin input level and has a control range of 0 to C8.5 db. ? single chip or master chip in a cascade connection h: gain control on l: gain control off h is recommended for echo cancellation. ? slave chip in a cascade connection fixed at l this pin is loaded in synchronization with the falling edge of the int signal or the rising edge of rst . reset signal. l: reset mode h: normal operation mode during initialization, input signals, except for pwdwn are disabled for 100 m s after reset (after rst is returned from l to h). input the basic clock during the reset. output pins during reset are in the following sates : high impedance: sout, rout, pd0 to 15 l: wdt h: of1 , of2 not affected: x2, synco, scko, irld , mcko transmit clock signal (200 khz) for the pcm codec. connect this pin to the sck pin and the pcm codec transmit/receive clock pin. not affected by reset. outputs "0" during power-down. leave it open if using an external sck. 8 khz sync signal for the pcm codec. connect this pin to the sync pin and the pcm codec transmit/receive sync pin. leave it open if using an external sync. test pin. leave this pin open. description symbol type synco o scko o rst i 24 40 25 41 27 44 28 45 wdt o 29 46 gc i pin 32-pin ssop 64-pin qfp
? semiconductor MSM7620 9/28 (5/5) description symbol type parallel data transfer flag. ? single chip fixed at h ? master chip in a cascade connection fixed at h ? slave chip in a cascade connection connect of2 of the master chip to the first stage slave chip. connect of1 of the previous stage slave chip to the second and later stage slave chips. refer to the control pin connection example. parallel data transfer flag. ? single chip leave this pin open. ? master chip in a cascade connection connect to the sf1 of all slaves. ? slave chip in a cascade connection connect to the sf2 of the next stage slave chip. connect the last stage slave chip to the sf1 of the master chip. refer to the control pin connection example. parallel data transfer flag. ? single chip connect of2 . ? master chip in a cascade connection connect of1 of the last stage slave chip. ? slave chip in a cascade connection connect of1 of master chip for all slave chips. refer to the control pin connection example. parallel data output flag. ? single chip connect to sf1 . ? master chip in a cascade connection connect to sf2 of the first stage slave chip. ? slave chip in a cascade connection leave open. refer to the control pin connection example. 60 of2 o 59 sf1 i 55 of1 o 54 sf2 i 32-pin ssop 64-pin qfp pin
? semiconductor MSM7620 10/28 absolute maximum ratings parameter power supply voltage input voltage power dissipation storage temperature symbol v dd v in p d t stg condition ta = 25c rating C0.3 to 7 C0.3 to v dd + 0.3 1 C55 to 150 unit v v w c recommended operating conditions parameter power supply voltage power supply voltage input high voltage input low voltage operating temperature range symbol v dd v ss v ih v il ta condition pins other than x1 min. 4.5 2.4 0 C40 unit v v v v c typ. 5 0 max. 5.5 v dd 0.8 85 x1 pin 3.5 v v dd electrical characteristics dc characteristics (ta = C40c to +85c) min. typ. max. unit condition symbol parameter 4.2 v dd v 0 0.4 v C100 C50 C10 m a 0.1 10 m a C100 C50 10 m a 3040ma 4 5ma 15 pf 20 pf 0.1 10 m a 6 8ma C10 C0.1 m a C10 C0.1 m a output high voltage output low voltage high level input current low level input current high level output current low level output current power supply current (operating) power supply current(stand-by) pwdwn ="l" input capacitance output load capacitance v oh v ol i ih i il i ozh i ozl i ddo i dds c i c load when oscillation circuit is used as basic clock v ol = v ss to v dd input other than the above pd15 to pd0 with pull-up v oh = v dd v il = v ss to v dd input other than the above sf1 , sf2 with pull-up i oh = 40 m a i ol = 1.6 ma v ih = v dd when extarnal input is used as basic clock
? semiconductor MSM7620 11/28 echo canceller characteristics (refer to characteristics diagram) r in = C10 dbm0 (5 khz band white noise) e. r. l. (echo return loss) = 6 db t d = 2 ms att, gc, nlp: off r in = C10 dbm0 (5 khz band white noise) e.r.l. = 6 db att, gc, nlp: off cancellable echo delay time for a slave chip in a cascade cancellable echo delay time for a single chip or a master chip in a cascade echo attenuation parameter symbol condition l res t d t ds min. typ. max. unit 30db 27 ms 31 ms
? semiconductor MSM7620 12/28 ac characteristics (ta = C40c to +85c) parameter clock frequency clock cycle time clock duty ratio clock "h" level pulse width clock "l" level pulse width clock rise time clock fall time sync clock output time internal sync clock frequency internal sync clock output cycle time internal sync clock duty ratio internal sync signal output delay time internal sync signal period internal sync signal output width transmit/receive operation clock frequency transmit/receive sync clock cycle time transmit/receive sync clock duty ratio transmit/receive sync signal period sync timing sync signal width receive signal setup time receive data input time irld signal output delay time irld signal output width serial output delay time fc = 18 mhz fc = 18 mhz fc = 18 mhz fc = 18 mhz fc = 18 mhz fc = 18 mhz symbol condition f c t mck t dmc t mch t mcl t r t f t dcm f co t co t dco t dcc t cyo t wso f sck t sck t dsc t cyc t xs t sx t wsy t ds t id t dic t wir t sd t xd min. 17.5 54.1 40 23.5 23.5 64 0.488 40 123 45 45 t sck 45 typ. 18.0 55.56 50 200 5 50 125 t co 50 125 7t sck t sck max. 18.5 57.1 60 5 5 100 5 2048 15.6 60 t cyc Ct sck 138 90 90 unit mhz ns % ns ns ns ns ns khz m s % ns m s m s khz m s % m s ns ns m s ns m s ns m s ns
? semiconductor MSM7620 13/28 ac characteristics (continued) (ta = C40c to +85c) parameter symbol condition min. typ. max. unit t wr 1 m s t drs 5ns t dre 52ns t dit 100 m s t dps 111 ns t dpe 15ns t dts 20ns t dth 120 ns t dsr 20ns t dhr 10ns t wpd 2t mck ns t df t mck ns t wfo t mck /2 ns t wfi ofz connected to sfx t wfo ns t fs 20 ns t fh 10 ns reset signal input width reset start time reset end time processing operation start time power down start time power down end time control pin setup time ( int ) control pin hold time ( int ) control pin setup time ( rst ) control pin hold time ( rst ) parallel data output signal width flag signal output time flag signal output width flag signal input width data read setup time data read hold time
? semiconductor MSM7620 14/28 timing diagram clock timing t r t f t mch t mcl fc. t mck x1/clkin t dcm scko scko synco fco. t co t dco t dcc t dcc t cyo t wso t dmc serial input timing sck sync sin rin msb msb t cyc fsck. t sck t sx t xs t wsy t ds t dsc 7 7 654321 lsb 0 t id t dic t dic irld t wir
? semiconductor MSM7620 15/28 serial output timing sck sync sout rout msb msb t cyc fsck. t sck t sx t xs t wsy t sd t dsc 7 7 654321 lsb 0 t xd t xd high-z high-z operation timing after reset rst internal operation t wr t drs *reset timing can be asynchronous processing start t dit reset initialization t dre note: int is invalid in the diagonally shaded interval. power down timing pwdwn internal operation *t dps processing start power down t dpe *input mck in the t dps interval.
? semiconductor MSM7620 16/28 control pin load-in timing int ( irld ) *t cyc nlp, hcl, att, adp, gc t dhr rst t wr t dsr nlp, hcl, att, adp, gc t dth t dts *refer to the serial input timing parallel output timing pd15 pd 0 output data t wpd t wfo of1 of2 C t df high-z high-z parallel input timing input data t fs t fh t wfi sf1 sf2 pd15 pd 0 C
? semiconductor MSM7620 17/28 how to use the MSM7620 the MSM7620 cancels the echo which returns to sin using the rin signal. connect the base signal to the r-side and the echo generated signal to the s-side. connection methods according to echos example 1: cancelling acoustic echo (to handle acoustic echo from line input) acoustic echo codec MSM7620 codec m -law m -law rout rin sin sout line input h aff + C + example 2: cancelling line echo (to handle line echo from microphone input) example 3: cancelling line echo in a cascade connection (to handle line echo from microphone input) codec MSM7620 codec m -law m -law rout rin sin sout line echo h aff + C + microphone input codec MSM7620 codec m -law m -law rout rin sin sout line echo h aff + C + microphone input master h aff slave pd0 - 15
? semiconductor MSM7620 18/28 example 4: cancelling of both acoustic echo and line echo (to handle both acoustic echo from line input and line echo from microphone input) acoustic echo codec MSM7620 codec m -law m -law rout rin sin rout line input h aff + C + aff + C + sout sin rin sout line echo microphone input for line echo for acoustic echo MSM7620
? semiconductor MSM7620 19/28 control pin connection example single chip connection nlp hcl adp att gc pwdwn rst nlp hcl adp att gc pwdwn rst int sf1 * sf2 * ms * C * pd 0 irld * of1 * of2 * pd15 +5 v asterisk * mark indicates a pin only for the MSM7620-011. nlp hcl adp att gc pwdwn rst nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 +5 v master chip nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 slave chip +5 v four-stage cascade connection master + (slave 3) nlp hcl adp att gc pwdwn rst nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 +5 v master chip nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 slave chip 1 +5 v nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 slave chip 2 +5 v nlp hcl adp att gc pwdwn rst int sf1 sf2 ms C pd 0 irld of1 of2 pd15 slave chip 3 +5 v two-stage cascade connection master + (slave 1)
? semiconductor MSM7620 20/28 internal clock generator circuit example MSM7620 x1/clkin x2 xtal r c1 c2 r xtal c1 c2 gnd gnd : 18 mhz : 1 m w : 27 pf : 27 pf
? semiconductor MSM7620 21/28 echo canceller characteristics diagram 0 10 20 30 40 40 30 20 10 0 erl vs. echo attenuation echo attenuation [db] erl. [db] measurement conditions rin input = C10 dbm 5 khz band white noise (0 dbm = 2.2 dbm0) echo delay time t d = 2 ms att, gc, nlp = off 0 10 20 30 40 C50 C40 C30 C20 C10 0 rin input level vs. echo attenuation echo attenuation [db] rin input level [dbm] 0 dbm = 2.2 dbm0 measurement conditions rin input: 5 khz band white noise echo delay time t d = 2 ms erl = C6 db att, gc, nlp = off 0 10 20 30 0 echo delay time vs. echo attenuation echo attenuation [db] echo delay time [ms] 200 150 100 50 measurement conditions rin input = C10 dbm 5 khz band white noise (0 dbm = 2.2 dbm0) 1 2 3 4 5 6 7chip erl = C6 db att, gc, nlp = off the second through seventh chips are connected in a cascade. C10
? semiconductor MSM7620 22/28 measurement system block diagram m -law rout rin sin sout codec rin input white noise generator level meter delay att t d echo delay time l. p. f. 5 khz a a pcm pcm m -law codec a a pcm pcm erl (echo return loss) msm7543 msm7543 MSM7620
? semiconductor MSM7620 23/28 application circuit bidirectional connection example sout rin nlp hcl adp att gc v dd v ss sin rout sck sync int irld pwdwn rst wdt 9 14 11 12 7 8 23 27 28 13 10 2 3 4 6 29 32 5 msm7543gs-vk pcmout pcmin ain+ vfro gsx sg sgc 23 6 21 1 13 12 sin c1 r2 r3 r1 ainC 22 bclock 15 rsync 11 pdn 10 tmc 19 rout r5 r4 r6 clk ext. sck ext. sync rst pwdwn mike input speaker output v dd ag xsync 14 dg 9 synco 24 scko 25 x1 20 x2 21 v ss 16 c4 + + 13 10 2 3 4 6 29 32 5 16 c8 sout rin nlp hcl adp att gc v dd v ss v ss MSM7620-001gs-k r12 sin rout sck sync int irld pwdwn rst wdt synco scko x1 x2 9 14 11 12 7 8 23 27 28 24 25 20 21 13 12 15 11 10 19 14 9 pcmout pcmin bclock rsync pdn tmc xsync dg ain+ vfro gsx sg sgc ainC v dd ag msm7543gs-vk 23 6 21 1 24 22 16 r10 r11 c5 r8 r9 r7 rin sout circuit input circuit output r8 > 20 k w r9 > 20 k w r10 = 2.2 k w r11 = 10 k w r12 = 10 k w r13 = 0-20 k w r14 = 0-20 k w c6 = 10 m f c7 = 0.1 m f c8 = 10 m f c9 = 1.0 m f c10 = 1.0 m f r1 > 50 k w r2 > 20 k w r3 > 20 k w r4 = 2.2 k w r5 = 10 k w r6 = 10 k w r7 > 50 k w c1 = 0.1 m f c2 = 10 m f c3 = 0.1 m f c4 = 10 m f c5 = 0.1 m f 8 for cancellation of circuit echo 32-pin ssop for cancellation of acoustic echo 32-pin ssop MSM7620-001gs-k 3 5 aoutC pwi 3 5 aoutC pwi 24 16 8 + c7 c6 c10 r13 c2 + c9 r14 c3
? semiconductor MSM7620 24/28 cascade connection example 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 45 13 12 15 11 14 10 19 10 15 12 13 44 38 1 2 3 4 5 46 41 40 35 36 47 48 62 16 sin rout sck sync rst pwdwn nlp hcl adp ms att gc scko synco x1 x2 v dd v dd v dd v ss sout rin pd15 pd14 pd13 pd12 pd11 pd10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 of2 sf2 of1 sf1 int irld wdt sin rout sck sync rst pwdwn nlp hcl adp ms att gc scko synco x1 x2 v dd v dd v dd v ss sout rin pd15 pd14 pd13 pd12 pd11 pd10 pd 9 pd 8 pd 7 pd 6 pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 of2 sf2 of1 sf1 int irld wdt 14 11 52 51 34 33 30 29 28 27 26 25 24 23 22 21 20 19 60 54 55 59 6 8 45 13 12 15 11 14 10 19 10 15 12 13 44 38 1 2 3 4 5 46 41 40 35 36 47 48 62 16 23 6 21 22 1 pcmout pcmin bclock rsync xsync pdm tmc pcmout pcmin bclock rsync xsync pdm tmc ain + msm7543gs-vk msm7543gs-vk master slave r1 r2 r3 c1 sin rout r4 r5 9 dg + c4 64-pin qfp 64-pin qfp rst pwdwn + c8 rin sout r7 r8 r6 r7 > 20 k w r8 > 20 k w r9 = 2.2 k w r10 = 10 k w r11 = 0-20 k w r12 = 0-20 k w c6 = 10 m f c7 = 0.1 m f c8 = 10 m f c9 = 1.0 m f c10 = 1.0 m f r1 > 50 k w r2 > 20 k w r3 > 20 k w r4 = 2.2 k w r5 = 10 k w r6 > 50 k w c1 = 0.1 m f c2 = 10 m f c3 = 0.1 m f c4 = 10 m f c5 = 0.1 m f dg r9 r10 c5 9 MSM7620-011gs-bk MSM7620-011gs-bk clk 23 6 21 22 1 24 vfro gsx ainC sg sgc v dd ag 5 3 aoutC pwi ain + vfro gsx ainC sg sgc v dd ag 24 5 3 aoutC pwi 16 8 16 8 + c7 c6 c10 r12 c2 + c9 r12 c3
? semiconductor MSM7620 25/28 recommendations for actual design 1. set echo return loss (erl) to be attenuated. if the echo return loss is set to be amplified, the echo can not be eliminated. refer to the characteristics diagram for erl vs. echo attenuation quantity. 2. set the level of the analog input so that the pcm codec does not overflow. 3. the recommended input level is -10 to -20 dbm0. refer to the characteristics diagram for the rin input level vs. echo attenuation quantity. 4. applying the tone signal to this echo canceller will decrease echo attenuation. if the tone signal is input to the sin pin during the time that a signal is input to the rin pin, this echo cancceller operates faultily. a signal must be input to either the rin pin or the sin pin. pins adp and hcl must be driver at "h" if the tone signal is input to the sin pin during the time that a signal is input to the rin pin. 5. for changes in the echo path (retransmit, circuit switching during transmission, and so on.), convergence may be difficult. perform a reset to make it converge. if the state of the echo path changes after a reset, convergence may again be difficult. in cases such as a change in the echo path, perform a reset when possible. 6. when turning the power on, set the pwdwn pin to 1 and input the basic clock simultaneous by with power on. if powering down immediately after power on, be sure first input 10 or more clocks of the basic clock. 7. after powering on, be sure to reset. 8. after the power down pin is changed to a "1" from a "0", be sure to reset. 9. if this canceller is used to cancel acoustic echoes, an echo attenuation may be less than 30 db.
? semiconductor MSM7620 26/28 explanation of terms attenuating function : this function prevents howling and controls the noise level with an attenuator for the rin input and sout output. refer to the explanation of pins (att pin). echo attenuation : if there is talking (input only to rin) in the path of a rising echo arises, the echo attenuation refers to the difference in the echo return loss (cancelled amount) when the echo canceller is not used and when it is used. echo attenuation = (sout level during through mode operation) C (sout level during echo canceller operation) [db] echo delay time : this is the time from when the signal is output from rout until it returns to sin as an echo or other similar device. acoustic echo : when using a hands free phone, and so on, the signal output from the speaker echoes and is input again to the microphone. the return signal is referred to as acoustic echo. telephone line echo : this is a signal which is delayed midway in a telephone line and returns as an echo, due to reasons such as a hybrid impedance mismatch. gain control function : this function prevents howling and controls the sound level by with a gain controller for the rin input. refer to the explanation of pins (gc pin). center clipping function : this function forces the sout output to a minimum value when the signal is below -57 dbm0. refer to the explanation of pins (nlp pin). double talk detection : double talk refers to a state in which the sin and rin signals are input simultaneously. in a double talk state, a signal outside the echo signal which is to be cancelled can be input to the sin input, resulting in misoperation. the double talk detector prevents such misoperations of the canceller. howling detection : this is the oscillating state caused by the acoustic coupling between the loud speaker and the microphone during hands free talking. howling not only interferes with talking, but can also cause in misoperation of the echo canceller. the howling detector prevents such misoperation and prevents howling. echo return loss (erl) : when the signal output from rout returns to sin as an echo, erl refers to how much loss there is in the signal level during rout. erl = (rout level) - (sin level of the rout signal which returns as an echo) [db] if erl is positive (rout > sin), the system is an attenuator system. if erl is negative (rout < sin), the system is an amplifier system.
? semiconductor MSM7620 27/28 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.83 typ. ssop32-p-640-0.80-k mirror finish
? semiconductor MSM7620 28/28 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp64-p-1414-0.80-bk package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.87 typ. mirror finish

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